1. Technical Field
Example embodiments relate generally to data signal receiver, and more particularly to data signal receiver enhancing a jitter correlation between data signal and clock signal, transceiver system including the same, and a method of receiving data signal with enhanced jitter correlation between data signal and clock signal.
2. Discussion of the Related Art
Recently, developing low-power & low-performance processors and linking the low-power & low-performance processors with high speed is evaluated as a better strategy on the processor market than developing one high-power & high-performance processor. It is necessary to develop a high-speed transceiver system among processors, between processor and memory, and between processor and peripheral component.
The transceiver system may have an embedded-clock architecture or a forwarded-clock architecture. The forwarded-clock architecture may be called as source synchronous parallel link (SSPL) architecture.
The embedded-clock architecture doesn't require a channel for a clock signal because it transfer only data signal through channels to other chips. But, the embedded-clock architecture requires a clock & data recovery (CDR) circuit to recover the clock signal from the data signal. Because of power consumption and execution time of the CDR circuit, the embedded-clock architecture is not appropriate to high-speed & low-power transceiver system.
The SSPL architecture transfers data signal and clock signal after synchronizing with a clock synthesizer. Because SSPL architecture does not require CDR circuit and a jitter of the data signal and a jitter of the clock signal has high correlation each other, the SSPL architecture is appropriate to high-speed & low-power transceiver system.
Problems blocking development of the SSPL architecture are amplification of clock signal jitter on the channel, generation of uncorrelated jitter on a clock distribution network (CDN), and a latency mismatch between the data signal and the clock signal. To solve the problems, a latency removing method and a clock signal jitter filtering method are proposed.
The latency removing method adds latency to the data signal as much as latency of the clock signal artificially. The latency removing method has advantage that latency difference between the data signal and the clock signal may be reduced, and the jitter correlation between the data signal and the clock signal may be increased. The latency removing method has disadvantage that power noise induced jitter in proportion to length of delay signal line occurs, and power consumption may be increased.
The clock signal jitter filtering method filters high frequency jitter component, which reduces correlation between the data signal and the clock signal, from the clock signal. Because the clock signal jitter filtering method uses oscillators having a filtering function, it is easy for implementation and consumes less power. The clock signal jitter filtering method has disadvantage that not all of the high frequency jitter components may be removed and the high frequency jitter component may be replaced with a phase noise.